Three-dimensional integrated circuits (3-D ICs) have been shown to reduce on-chip global interconnect lengths and thus alleviate delay and power consumption problems. 3-D ICs can also facilitate the integration of dissimilar technologies (digital, analog, radio-frequency circuits, et al.). In a 3-D IC, multiple active layers or substrates are vertically stacked on top of each other and are interconnected using “short” vertical links These “short” vertical links are referred to as through-silicon vias. Despite being “short”, through-silicon vias have high aspect ratios: the radius of a through-silicon via may be in the order of several micrometers while its length is usually over 50 micrometers.
As fabrication technologies for through-silicon vias have progressed, accurate and efficient techniques for through-silicon via admittance extraction are needed for performance evaluation of circuits and systems built in 3-D ICs and for design optimization of 3-D IC interconnections. Conventional admittance extraction techniques may not be able to account for the unique location, size, and shape of through-silicon vias. For example, a significant portion of a through-silicon via is located inside the silicon substrate, increasing substrate effects significantly. The substrate effects may make the admittance a function of frequency. Some of the substrate effects are nonlinear due to the semiconductor nature of the substrate, which may cause the admittance to become bias-voltage dependent. These substrate effects may not be efficiently considered by conventional techniques. There have been efforts and interest that try to problems like the above. However, challenges remain in developing through-silicon via admittance extraction techniques that offer a good mix of speed, accuracy and generality.